Staff RTL Design Engineer

Acceler8 Talent has partnered with a well-supported data center acceleration company that is actively searching for a driven Staff ASIC Design Engineer.

This company is deeply committed to developing a novel interconnect architecture aimed at resolving congestion challenges within extensively distributed systems. Their recent successful completion of a significant Series B funding round serves as a strong indicator of their growth and potential.

The company's founding members bring substantial expertise from distinguished hardware and technology enterprises. Notably, their primary investor boasts an admirable track record of nurturing early-stage startups into prosperous and thriving enterprises.

They are currently seeking an engineer with a high level of expertise with large, complex, SoCs.

If you are located in the San Francisco Bay Area, Austin, TX, Raleigh, NC, or Boston, MA, area this company is offering a fully remote position.

Roles and Responsibilities:

• Lead all stages of the design process, from tradeoff analysis and specification to RTL implementation.
• Deliver high-performance designs that meet timing, area, reliability, testability, and power targets set by the engineering team.
• Collaborate with system software, architecture, and microarchitecture teams to develop high-throughput engines for data processing, movement, storage, and scheduling.
• Support functional verification, including strategy development, test planning, and execution.
• Ensure product meets performance demands across diverse data center use cases.
• Assist with silicon bring-up and post-silicon testing of critical functions.

Skills/Qualifications:

• Proven experience designing high-performance interface logic or processing pipelines (e.g., PCIe, CXL, NV-Link, Ethernet, Infiniband) in advanced silicon geometries.
• Preferred experience with PCIe Gen5/6 and CXL at the Transaction Layer.
• Expertise in designing multi-threaded datapaths and blocks like DMA controllers and queueing engines.
• Strong knowledge of SystemVerilog.
• Proficiency in Python, Perl, or other scripting languages.

Experience:

• Junior: BSEE/CE + 3 years or MSEE/CE + 2 years.
• Mid: BSEE/CE + 7 years or MSEE/CE + 5 years.

If you feel this is relevant to your skillset and the work you have done in the industry please apply here. If you don't have any experience with large, complex SoCs please do not apply.