Lead RTL Design Engineer
- US$250000 - US$300000 per annum + Equity Package
- Mountain View, California
- Permanent
Acceler8 Talent has partnered with a series C startup company that has created an innovative software-defined architecture providing scalable performance, enabling real-time computing for a range of critical and complex applications.
They are actively looking for a hands on Principal/Lead RTL Design Engineer who will report directly to the VP of Hardware.
This advanced technology improves power efficiency and reduces latency while significantly enhancing computing capabilities for large datasets, whether processed at the edge or in the cloud. Key applications include accelerating encryption techniques, such as Fully Homomorphic Encryption (FHE), to enable real-time computation on encrypted data, supporting data privacy and security.
Founded by a well known name in the industry this company has closed their series C, taped out their first chip, and is currently in the process of taping out their second, more complex chip.
About the Role
We're looking for an experienced RTL Design Engineer to lead the creation of advanced digital hardware designs. In this role, you'll manage the design and implementation of RTL components for complex systems and collaborate with system architects, verification, physical design, and software teams to deliver high-quality designs that meet performance, power, and area goals.
Key Responsibilities:
- RTL Design: Oversee RTL design from concept to implementation, synthesis, and verification.
- Team Leadership: Mentor RTL designers and promote team growth.
- Documentation: Maintain design specifications and interface documents.
- Optimization: Optimize designs for power, performance, and area (PPA); collaborate with physical design.
- Collaboration: Work with system architects and verification teams for a cohesive design flow.
- Simulation & Debugging: Run test benches, simulations, and debug at various levels.
- Timing Closure: Partner with physical design to ensure timing requirements.
- Low Power Design: Implement power-saving techniques and write UPFs.
- Design Reviews: Lead design reviews, providing expertise on trade-offs.
- Compliance: Ensure designs meet industry standards and functional safety.
Required Qualifications:
- Experience: 10+ years in RTL design; 3+ in leadership.
- Education: Bachelor's or Master's in Electrical/Computer Engineering.
- Skills: Proficient in Verilog/SystemVerilog/VHDL and EDA tools (e.g., Synopsys, Cadence).
- Knowledge: Strong digital design principles, FSMs, and CDC.
- Debugging: Skilled with simulation tools and waveform viewers.
- PPA Optimization: Expertise in PPA trade-offs.
- Communication: Strong communication skills for cross-functional collaboration.
Preferred Qualifications
- Experience with high-speed interfaces (e.g., Arteries NoC, NIU, RISC-V).
- Exposure to ASIC/FPGA prototyping and low-power design.
- Familiarity with scripting (Python, Perl, TCL).
- Knowledge of machine learning accelerators, GPUs, or custom processors.
Please reach out to Jwhitcomb@acceler8talent.com if you fit the qualifications and are ready to take charge of an impressive design team.