Design Verification Engineer
None3
Posted: 13/12/2024
- $200,000-$280,000
- Bay Area
- Permanent
Acceler8 Talent is working with the most exciting up & coming startup company that is developing specialized AI chips tailored for specific model architectures. They are looking for a expert Design Verification Engineer. Their initial product focuses exclusively on transformer models, delivering significantly higher throughput and lower latency compared to traditional solutions.
With our ASIC technology, you can create applications that would be unfeasible with standard GPUs, such as real-time video generation and advanced deep reasoning capabilities.
Job Duties:
- Develop ASIC testbenches using UVM to verify microchip design functionality.
- Implement micro-architecture and RTL specifications in System Verilog for AI microchips, managing test scenarios and coverage plans.
- Perform functional and performance verification using synthesized netlists, coverage models, and tools like Synopsys VCS and Verdi, in collaboration with design and architecture teams.
- Apply static and dynamic methods for timing closure, including static timing analysis and result analysis.
- Use formal verification tools for RTL and gate-level netlist equivalence checking, resolving mismatches with the design team.
- Define and implement assertions and checkers to ensure correct functionality and signal integrity at module and chip levels.
- Debug microchips using waveforms and logs, working with the design team to resolve issues.
- Write Python scripts to automate verification tasks, including testbench generation, test case creation, and results analysis.
- Participate in verification meetings, track issues, and follow up on required actions.
- Document and report verification progress, coverage, and signoff, ensuring up-to-date documentation.
Minimum Requirements:
- Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
- 5 years of experience as a Hardware Engineer, Silicon Engineer, ASIC Design Verification Engineer, or related role.
- 2 years of experience with:
- UVM (Universal Verification Methodology)
- Testbench development
- Synopsys VCS
- System Verilog
- AXI (Advanced eXtensible Interface)
- ASIC Development
If you are ready to join one of the top startup companies in the world within the next month. Please apply here or reach out to Jwhitcomb@acceler8talent.com
Jake Whitcomb
Recruitment Executive